I spent some time the last couple of weeks researching large scale chip-level testing. I needed some information for a new project, so I dug around online.
I'm no stranger to wafer-level testing or semiconductor issues - I've been doing that for many years now. But after digesting the information I found on , I have to say two things. One, the test issues those guys face are out of my current jurisdiction. Two, it's pretty cool stuff (see also here) and I'm enjoying learning more about it.
If you want to do some more digging on your own, I would suggest starting with Chip Scale Review and spread out from there. Also, take a look at this definition of automated test patterns as well as the interface language some large test systems use.
"Today, my jurisdiction ends here. Pick up my hat."